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Browsing by Author Mehta, Usha

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PreviewIssue DateTitleAuthor(s)
ITFEC022-9.pdf.jpgApr-2014Advanced ATPG Based On Fan, Testability Measures And Fault ReductionDhare, Vaishali; Mehta, Usha
ITFEC010-22.pdf.jpgMar-2011Analysis of Don’t Care Bit Filling Techniques for Optimization of Compression and Scan PowerBhavsar, K. A.; Mehta, Usha
ITFEC010-9.pdf.jpg9-Dec-2010Analysis of Test Data Compression Methods Using Huffman CodesBhavsar, Kinjal A.; Mehta, Usha
ITFEC022-7.pdf.jpg25-Nov-2009Application of CORDIC Algorithm for Sine-Cosine ComputationJoshipura, Himali; Dhare, Vaishali; Mehta, Usha
ITFEC010-7.pdf.jpg8-Dec-2011Artificial Intelligence Based Scan Vector Reordering for Capture Power MinimizationMehta, Usha; Dasgupta, Kankar S.; Devashrayee, N. M.; Parmar, Harikrishna
ITFEC010-5.pdf.jpg6-Dec-2010Combining Unspecified Test Data Bit Filling Methods and Run Length Based Codes to Estimate Compression, Power and Area OverheadMehta, Usha; Dasgupta, K. S.; Devashrayee, N. M.
ITFEC022-4.pdf.jpg23-Apr-2010Controllability and Observability Algorithm for 10-fanin-fanout Combinational CircuitsDhare, Vaishali; Mehta, Usha
ITFEC022-12.pdf.jpgMar-2016Defect Analysis Of Quantum-Dot Cellular Automata Combinational Circuit Using HDLQDhare, Vaishali; Mehta, Usha
ITFEC022-11.pdf.jpg26-Jun-2015Defect characterization and testing of QCA devices and circuits: A surveyDhare, Vaishali; Mehta, Usha
ITFEC010-18.pdf.jpgNov-2014Design and Implementation of 2-Axis Circular Interpolation Controller in Field Programmable Gate Array (FPGA) for Computer Numerical Control (CNC) Machines and RoboticsSaifee, Mufaddal A.; Mehta, Usha
ITFEC010-19.pdf.jpgSep-2014Design And Implementation Of 3-Axis Linear Interpolation Controller In Fpga For CNC Machines And RoboticsSaifee, Mufaddal A.; Mehta, Usha
ITFEC010-1.pdf.jpg2008Design and Implementation Of Complete Test Set Generator using ATPG and Fault CoverageMehta, Usha; Pedhadiya, Mittal
ITFEC010-12.pdf.jpg25-Nov-2009Design and Implementation Of RAM Based Shift RegisterVasava, Hiren J.; Mehta, Usha
ITFEC010-2.pdf.jpg30-Nov-2006Design and Implementation of Sigma Delta DACMehta, Usha; Patel, Jayesh
ITFEC010-11.pdf.jpg25-Nov-2009Design of Convolution Encoder in 0.35μ CMOS TechnologyUpadhyay, Sarang; Patel, Nilesh K.; Mehta, Usha
ITFEC010-10.pdf.jpg25-Nov-2009Design of Universal Asynchronous Receiver Transimitter in 0.35μm CMOS TecnologyPrajapati, Sanjay B.; Gandhi, Priyesh P.; Malek, Mohammed Zuber P.; Mehta, Usha
ITFEC006-9.pdf.jpgApr-2012Design Simulation And Characterisation Of Op-Amp Based 3 Bit R-2r Segmented DacsSoni, Rajanikant; Amin, Gireeja; Devashrayee, N. M.; Mehta, Usha
ITFEC022-5.pdf.jpg23-Jul-2010Development of Controllability Observability Aided Combinational ATPG with Fault ReductionDhare, Vaishali; Mehta, Usha
ITFEC010-16.pdf.jpgJan-2014Error Resilience In Case Of Test Data Compression Technique For IP Core Based SocMehta, Usha; Trivedi, Rakesh G.; Thaker, Nandish B.
ITFEC022-10.pdf.jpg19-Dec-2015Fault Analysis of QCA Combinational Circuit at Layout & Logic LevelDhare, Vaishali; Mehta, Usha
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