1. DSpace at Nirma University
  2. 02. Institute of Technology
  3. Electronics and Communication Engineering Department

Dissertation, EC (VLSI) : [423] Collection home page

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Collection's Items (Sorted by Submit Date in Descending order): 201 to 220 of 423
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PreviewIssue DateTitleAuthor(s)
14MECV02.pdf.jpg1-Jun-2016Standard Cell Design And Libraries DevelopmentWaghide, Aniket
14MECV01.pdf.jpg1-Jun-2016Circuit Simulation/Reliability Verification TPT and Efficiency Improvements in Tool/flow For Analog And Memory IpsAgarwal, Simple
13MECV01.pdf.jpg1-Jun-2015Development & Verification of Standard CellBhavsar, Stefi
13MECV31.pdf.jpg1-Jun-2015Development of Verification Environment for Behavioural Models of Analog Mixed Signal IP PLLNarang, Sahil
13MECV30.pdf.jpg1-Jun-2015Design and Characterization of High Speed 10T SRAM and Analysis of Memory CompilerShah, Hetansh
13MECV29.pdf.jpg1-Jun-2015Design & Characterization Of HD1P and HS1P Memory CompilerVaghasia, Prashantkumar
13MECV28.pdf.jpg1-Jun-2015Physical View Generation and Validation of AMS IPS for the SOC EnablementThummar, Nileshkumar
13MECV26.pdf.jpg1-Jun-2015Validation Of Unified Power Format and Low Power FeaturesShah, Varun
13MECV25.pdf.jpg1-Jun-2015Development of Verification IP for CAN Controller Using UVMShah, Ravin
13MECV22.pdf.jpg1-Jun-2015Verification Component Development for Interlaken ProtocolRabadiya, Vipul
13MECV20.pdf.jpg1-Jun-2015Margin Analysis of Memory Compiler for FinFET TechnologyPatel, Yogesh
13MECV19.pdf.jpg1-Jun-2015Assertion based Verification of STBUSPatel, Vaishaliben
13MECV18.pdf.jpg1-Jun-2015Development And Valiation Of MBIST IPPatel, Vaibhav
13MECV17.pdf.jpg1-Jun-2015Modeling and Verification of Power Aware IO ModelsPatel, Ronak
13MECV16.pdf.jpg1-Jun-2015Performance Evaluation of SRAM Memory CompilerPatel, Anuj
13MECV15.pdf.jpg1-Jun-2015Analysis and Characterization of Low Power SRAM Memory CompilerPadaliya, Madhav
13MECV14.pdf.jpg1-Jun-2015Verification Of Analog Ip: Power Management Unit (PMU)Niranjani, Mayankkumar
13MECV12.pdf.jpg1-Jun-2015Advance Automated Mechanism for Design, Compilation Verification and Validation Flows of Complex SoC DesignSharma, Ankur
13MECV11.pdf.jpg1-Jun-2015Front-end ASIC Design and Verification of Programmable and Precision Delay Timing Generator for CCD DetectorsMehta, Urvi
13MECV10.pdf.jpg1-Jun-2015Bit Cell Architecture For Embedded RomMasrani, Mansi
Collection's Items (Sorted by Submit Date in Descending order): 201 to 220 of 423
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