DSpace at Nirma University: Dissertation, EC (VLSI)

Dissertation, EC (VLSI) : [423] Collection home page

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Collection's Items (Sorted by Submit Date in Descending order): 221 to 240 of 423

Issue Date	Title	Author(s)
1-Jun-2015	Improving Efficiency and Effectiveness of IP and AArch32 Compliance Verification for v8-A CPUs	Shelat, Malav
1-Jun-2015	Test Content Development For Next Generation Graphics	Joshi, Mrunmayee
1-Jun-2015	Automation of Design Flow for Efficient Implementation of Latch Repeater Functional Blocks in Custom Design Approach	Jirawala, Hardik
1-Jun-2015	Study of Electro-migration (EM) on Full Custom VLSI SRAM Designs and Development of an EM Assessment Methodology for Memory Compilers	Dhonde, Anand
1-Jun-2015	Semi-Custom Design Of Functional Blocks For Microprocessor Core With Timing, Power And Area Optimization	Desai, Parth
1-Jun-2015	Design And Characterization Of Memory Compiler And Enhancing Bitcell Performance With CNTFET For IOT Applications	Desai, Ishita
1-Jun-2015	6T-SRAM Cell Leakage Current Analysis & Self-Timing Circuit in the Memory	Dave, Rachit
1-Jun-2015	Validation of Mixed Signal IP building Blocks	Dabhi, Dushyantsinh
1-Jun-2014	Design and Simulation of Low Power Low Noise Analog Front End for Digital Hearing Aid	Panchal, Dipesh J.
1-Jun-2014	Next Generation Rtl Simulation Technology For Graphics Design	Savalia, Abhishek D.
1-Jun-2014	Functional veri cation of Memory controller for LPDDR of 333 MHz using UVM	Patel, Alay Gopalbhai
1-Jun-2014	Interface Circuit Design for MEMS Based Piezoresistive Accelerometer	Parashar, Ashish Kumar
1-Jun-2014	Low Power Design And Verification of Module Solution	Bhimani, Vishal S.
1-Jun-2014	Physical Design Of Function Unit Block Using Random Logic Synthesis Methodology	Savaj, BrijeshKumar
1-Jun-2014	Design and Verification of DDR IP Memory Controller	Gajjar, Sanket
1-Jun-2014	Optimization in IO Characterization Methodology	Gandhi, Jigar B.
1-Jun-2014	PDK (Process Design Kit) Backend Validation	Godhani, Dhaval M.
1-Jun-2014	Verification Methodologies For Memory BIST	Parihar, Kunal
1-Jun-2014	Challenges In Subsystem Verification	Lahoti, Pravin Kumar Omprakash
1-Jun-2014	SoC Development Containing the Teststructures for SiVal of Memories/IO's/Efuses/Standard Cells	Lalani, Gaurav A.

Collection's Items (Sorted by Submit Date in Descending order): 221 to 240 of 423

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