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Browsing by Subject VLSI 2014

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PreviewIssue DateTitleAuthor(s)
14MECV29.pdf.jpg1-Jun-2016Accuracy And Runtime Improvement Techniques For Power Characterization Of Compiled Memory Arrays For Soc PlatformsUpadhyaya, Tanvi
14MECV21.pdf.jpg1-Jun-2016Advanced Routing Algorithm for FUB IntegrationPatel, Priya
14MECV20.pdf.jpg1-Jun-2016Advanced Techniques Of DFT SimulationPatel, Pooja
14MECV01.pdf.jpg1-Jun-2016Circuit Simulation/Reliability Verification TPT and Efficiency Improvements in Tool/flow For Analog And Memory IpsAgarwal, Simple
14MECV25.pdf.jpg1-Jun-2016Delay Locked Loop For High Speed Serial InterfaceRamani, Ashish
14MECV18.pdf.jpg1-Jun-2016Design And Validation Of Mrepair Ip In 45nm TechnologyPatel, Maitri
14MECV14.pdf.jpg1-Jun-2016Design Verification and Gate Level Power Analysis of Turbo DecoderPatel, Axay
14MECV12.pdf.jpg1-Jun-2016Development and Validation of Memory Built In Self Test (MBIST) IPMonpara, Dhruvik
14MECV22.pdf.jpg1-Jun-2016Development of Advance ATPG Using Probabilistic ApproachPatel, Tarak
14MECV13.pdf.jpg1-Jun-2016Development Of Utilities To Measure Effectiveness Of Tests Generated By MP RIS ToolPandit, Vivekkumar
14MECV30.pdf.jpg1-Jun-2016DFT Verification and Pattern Simulation for Analog IPPatel, Urmish
14MECV08.pdf.jpg1-Jun-2016Electrically Aware Design Flow for Sub-micron TechnologiesJoshi, Jagrut
14MECV15.pdf.jpg1-Jun-2016Enhancement of HDL Based Memory ModelsPatel, Jinisha
14MECV05.pdf.jpg1-Jun-2016Evaluation And Deployment Of Standalone Memory CharacterizationGhelani, Chaitanya
14MECV11.pdf.jpg1-Jun-2016Extracted Timing Model Generation & IR Drop Analysis at Advance Technology NodeTripathi, Mohit
14MECV04.pdf.jpg1-Jun-2016Hierarchical Timing Analysis Convergence Of Soc Using Hyperscale MethodologyBhadada, Chetana
14MECV24.pdf.jpg1-Jun-2016Highly Optimized 2-Step Design Validation and Integration System Delivery to a Multicore ProjectKhullar, Poornima
14MECV09.pdf.jpg1-Jun-2016Impact of IEEE 1801 on Design for TestabilityParakh, Kshama
14MECV06.pdf.jpg1-Jun-2016Impact of Micro-Architectural Optimizations on Post Layout PowerJitender
14MECV07.pdf.jpg1-Jun-2016Low Power Static and Dynamic Checks for LTE ModemJoshi, Harshita
Showing results 1 to 20 of 30  next >