1. DSpace at Nirma University
  2. 02. Institute of Technology
  3. Electronics and Communication Engineering Department

Dissertation, EC (VLSI) : [423] Collection home page

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Collection's Items (Sorted by Submit Date in Descending order): 161 to 180 of 423
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PreviewIssue DateTitleAuthor(s)
15MECV09.pdf.jpg1-Jun-2017FPGA Based CCD Timing GeneratorSharma, Ekta
15MECV08.pdf.jpg1-Jun-2017FPGA Implementation of Digital Beam Former for Synthetic Aperture Radar (SAR) ApplicationDohare, Parul
15MECV07.pdf.jpg1-Jun-2017At-Speed ATPG Aware Scan StitchingDave, Dipen
15MECV06.pdf.jpg1-Jun-2017Optimal Methodology for Signal Integrity based Timing and Noise Analysis of IP’s and IP Interface ModelingChoudhari, Manju Ambaram
15MECV05.pdf.jpg1-Jun-2017Logical Convergence of High Speed Design using Formal VerificationChokshi, Raj
15MECV04.pdf.jpg1-Jun-2017Timing Model Validation To Reduce Turn Around TimeBiyani, Adarsh
15MECV03.pdf.jpg1-Jun-2017Scan Analysis & Coverage Improvement forLeading ProcessTechnologyBhatelia, Savan Hiren
15MECV02.pdf.jpg1-Jun-2017Methodology For Silicon Qualification Of Standard Cells: Design, Verification And Silicon DebugAgrawal, Ankita
15MECV01.pdf.jpg1-Jun-2017Strategies & Methodology Addressing Low Power Design ChallengesGang, Aditi
16MECV03.pdf.jpg1-May-2018Novel Physical Design Methodology for Efficient Power Optimization in SoC’s Server PartitionsChauhan, Atmiya Jatanbhai
16MECV02.pdf.jpg1-May-2018Design and Analysis of Power Efficient Dual Rail MethodologyBhatt, Kunjan Mukeshkumar
16MECV01.pdf.jpg1-May-2018How to Validate Machine Check Architecture Complete Flow at Full Chip LevelBaladaniya, Ketan
14MECV08.pdf.jpg1-Jun-2016Electrically Aware Design Flow for Sub-micron TechnologiesJoshi, Jagrut
14MECV30.pdf.jpg1-Jun-2016DFT Verification and Pattern Simulation for Analog IPPatel, Urmish
14MECV29.pdf.jpg1-Jun-2016Accuracy And Runtime Improvement Techniques For Power Characterization Of Compiled Memory Arrays For Soc PlatformsUpadhyaya, Tanvi
14MECV28.pdf.jpg1-Jun-2016PCell Development and Validation & Automation of FQA LVS Test Suite Development Using SKILL ScriptingMundra, Sourabh
14MECV27.pdf.jpg1-Jun-2016Power Reduction Evaluation of High Speed Cores Including Automation for P&R Productivity EnhancementShah, Nishchint
14MECV26.pdf.jpg1-Jun-2016Verification of Power Management Unit (PMU)Pambhar, Ravi
14MECV25.pdf.jpg1-Jun-2016Delay Locked Loop For High Speed Serial InterfaceRamani, Ashish
14MECV24.pdf.jpg1-Jun-2016Highly Optimized 2-Step Design Validation and Integration System Delivery to a Multicore ProjectKhullar, Poornima
Collection's Items (Sorted by Submit Date in Descending order): 161 to 180 of 423
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